Many processes are known in the art for simultaneously forming bipolar and complementary metal-oxide semiconductor devices (hence the term BiCMOS) on a single substrate. The resulting chips can be utilized in a manner which exploits the different advantages of the bipolar and field-effect transistors. The field-effect transistors can be used, for example, in a manner which takes advantage of their recognized low power requirements, while the bipolar devices can be used for applications requiring high switching speeds and/or relatively higher driving power.
One disadvantage inherent in many of the known BiCMOS processes is the inability to yield high-performance devices of both the bipolar and field-effect type. Processes which have been optimized for manufacturing bipolar devices, for example, typically yield low performance field-effect devices. The converse is true for processes optimized to make field-effect devices. Processes which attempt to optimize both device types are typically complex and difficult to implement.
In attempting to provide simplified BiCMOS processes which yield high-performance devices, it has become known in the art to define MOS gates and bipolar emitter and/or collector contacts from a single layer of poly-conductive material. U.S. Pat. No. 4,752,589 to Schaber, for example, utilizes a single layer of polysilicon to define both the MOS gates and the bipolar emitter contact. U.S. Pat. No. 4,818,720 to Iwasaki shows a method wherein the MOS gate electrodes and the bipolar emitter and collector contacts are defined from a single layer of polysilicon.
It is desirable in the art to provide a BiCMOS process which is compatible with conventional semiconductor processing techniques, which is not unduly complex or expensive, and which yields high-performance devices of both the bipolar and field-effect type.